Saleae Logic16

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The Saleae Logic16 is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

The case requires a Torx T5 screwdriver to open.

See Saleae Logic16/Info for more details (such as lsusb -v output) about the device.

See Saleae Logic for the predecessor product of the Saleae Logic16.

Hardware

Pinouts and connections:

JTAG header (FPGA):

The J3 pin header is a JTAG connector wired to the FPGA. The pins are (from left to right, the right-most pin, pin number 1, is square):

| | |5|4|3|2|1| |GND|TMS|TCK|TDO|TDI|

Testpoints:

| | |T1|T2|T3| |1.2V|3.3V|GND (FX2)|

Cypress FX2:

Other FPGA connections:

| | |28|CH0|52|CH8| |29|CH1|56|CH9| |32|CH2|57|CH10| |33|CH3|60|CH11| |34|CH4|61|CH12| |36|CH5|62|CH13| |43|CH6|64|CH14| |50|CH7|65|CH15| |73|LED (active low)|

Photos

Device, front

Device, bottom

PCB, top

PCB, bottom

Xilinx XC3S200A

Cypress FX2LP

I2C EEPROM

ST DVIULC6-4SC6

Voltage regulators

N-MOSFETs

Firmware

Firmware and FPGA bitstream usage

To use the Saleae Logic16 (or its clones) with sigrok, you must first use a Python script to extract the FX2 firmware and the FPGA bitstreams from version 1.2.10 of Saleae's Logic software.

First download the Saleae vendor software. This version has been tested to work, but more recent versions are not supported currently (see bug #989 ). Old Saleae vendor software versions can be downloaded from support.saleae.com . (32-bit vs 64-bit download doesn't matter; both produce the same output.)

Then extract the Logic Linux binary from the zip file and use the sigrok-fwextract-saleae-logic16 tool to extract the files from it. On Windows, this Python script can be run from python.exe . On Linux, it can be executed directly:

$ sigrok-fwextract-saleae-logic16 Logic saved 5214 bytes to saleae-logic16-fx2.fw saved 149516 bytes to saleae-logic16-fpga-18.bitstream saved 149516 bytes to saleae-logic16-fpga-33.bitstream

Copy these files to the directory where your libsigrok installation expects them and they will be found and used automatically by the libsigrok saleae-logic16 driver.

On Linux, this is usually /usr/local/share/sigrok-firmware or /usr/share/sigrok-firmware. The latter is correct on Ubuntu (and where files are created by the unrelated sigrok-firmware-fx2lafw package ).

On Windows, they should be placed in C:\Program Files\sigrok\PulseView\share\sigrok-firmware\.

On macOS, they should be placed in /[…]/PulseView.app/Contents/share/sigrok-firmware/.

Technical firmware details

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order.

See Saleae Logic16/Firmware for more details on the vendor firmware.

Driver

In Windows, the USB driver must also be installed using Zadig , similar to other devices, or you will get sr: saleae-logic16: Failed to init device.

Protocol

Sample format:

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

Configuration:

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

Channel number configuration
3 channels
6 channels
9 channels
16 channels
Sampling frequency
500kHz
1MHz
2MHz
4MHz
5MHz
8MHz
10MHz
12.5MHz
16MHz
25MHz
32MHz
40MHz
50MHz
80MHz
100MHz

Resources